Electrical sampling arrangement

ABSTRACT

A circuit for sampling a continuous repetitive waveform which includes an input gate, a memory device to store a signal related to the gated input signal, and a feedback path from the memory device to the gate in order to ensure that only variations in the sampled signal are transmitted to the memory device, the intervals between the instants of sampling being so arranged that a signal may be obtained from the memory device representative of a cycle of the waveform.

United States Patent [72] Inventor Robin T. Smith-Saville [56] References Cited Cambridge, England UNITED STATES PATENTS $55;- 12*?1 3,229,212 l/1966 Rogers 32s/151x 9 47 4s Patented Feb. 16, 1971 4259 10/1969 Rdgers 307/238 [73] Assignee Cambridge Consultants Limited Exammer- Donald orr Cambridge, England Assistant ExaminerB. P. Davis [32] Priority Apr. 17, 1967 Attorney-Cushman, Darby and Cushman [3 3] Great Britain [31] 17546/67 [54] M E ARRANGEMENT ABSTRACT: A circuit for sampling a continuous repetitive 10 C rawmg waveform which includes an input gate, a memory device to [52] -U.S. Cl 307/246, store a signal related to the gated input signal, and a feedback 307/227 307/238, 307/286, 307/322, 328/151 path from the memory device to the gate in order to ensure [51] Int. Cl. l-l03k 5/00, that only variations in the sampled signal are transmitted to H03k 17/00, H03! 3/68 the memory device, the intervals between the instants of sam- [50] Field of Search 318/151; pling being so arranged that a signal may be obtained from the 307/238, 286, 322, 246, 227; 330/30 (D) memory device representative of a cycle of the waveform.

TIME 3 4 s n/c. Put. :5

l GENERATOR 2 5 5 7 Q 8 Mall 10 12 I wrur IMPfDA/VCE AMPLIFIER D/FFEEE/Y 7/4 1 AMPL/F/EIZS 7 Zo 2 7 SAM/ 2 14 5 2 1\ 22 23 FEEDBA Ck .4 75 m m 1 4 MPL lF/EE VIRTUAL EAR) H 1 wee-pan CK AMPLIFIER i 1 ELECTRICAL SAMPLING ARRANGEMENT This invention relates to a method of and apparatus for sampling a continuous repetitive waveform.-

Oscilloscopes controlled by built-in time bases are commonly used for displaying repetitive waveforms for the purposes of observation and waveform analysis. However, the upper frequency limit for even the best Oscilloscopes is about 100 MHz and a typical rise time which can be handled is 8to IlO nanoseconds. Thus, for the purpose of displaying very much higher frequencies and pulses with faster rise times a different technique is required. v

The present invention provides both a method of and an apparatus employing a novel technique for sampling a continuous repetitive waveform which enables signals to be produced which can be used in displaying a waveform.

According to one aspect of the present invention, there is provided a method 'of sampling a continuous repetitive waveform which includes the steps of sampling the waveform at successive instants of time, storing a signal based upon a first sample, and varying the stored signal in accordance with the difference between the said stored signal and a signal related to a successive sample, whereby an output is provided which corresponds in amplitude to successive points in a cycle of the waveform.

According to a further aspect of the invention, there is provided an apparatus for sampling a continuous repetitive waveform at successive instants .of time which includes a differential gate to an input of which the waveform is applied, a memory device connected to an output from the gate, a feedback from the memory device to a second input to the gate, and control means to open the gate-at the successive instants whereby an output is obtained from the gate which is dependent upon the difference in amplitude between successive samples and an output is obtained from the memory device which corresponds in amplitude to successive points in a cycle of the waveform. I

The employment of this sampling technique enables repetitive waveforms to be displayed which have very much higher frequencies and faster rise times than would otherwise be possible. i

Embodiments in accordance with the present invention will now be described with reference to the accompanying drawings, in which:

FIG. 1 shows a block schematic diagram of a circuit arrangement of a waveform sampling apparatus,

FIG. 2 shows a block schematic diagram of a time base arrangement, employed in the apparatus of FIG. 1,

FIGS. 3 and 4 show schematic diagrams of monostable circuits for use in the time base shown in FIG. 2,

FIGS. 5a and 5b show an example ofa known amplifier arrangement and an amplifier arrangement suitable for use in the apparatus of FIG. I respectively, 7

FIGS. 6a and 6b illustrate gated differential amplifier arrangements suitable for use in theapparatus of FIG. 1, and

FIG. 7 shows a sawtooth waveform generator circuit arrangement. I

Referring to the drawings, there is shown in FIG. 1 a circuit having an input terminal 1 to which a continuous repetitive waveform may be applied. The waveform is applied directly from the terminal 1 to a sampling gate 2 and sampling impulses derived from the-input by a time base arrangement 3 for controlling the sampling instants are also applied over a lead 4 to the sampling gate 2. The output from the sampling gate is applied over a lead 5 to a differential amplifier 6, and the output from the amplifier 6 is applied via a capacitor 7 to an input of a second differential amplifier 8. A second input for the differential amplifier 8 is obtained from a synchronizing pulse generator 9 and a third input to the differential amplifier 8 is obtained as a feedback from the output of the amplifier via a memory capacitor C,, across a resistor R1. A signal from the memory capacitor C,, is also applied to a high-input impedance noninverting amplifier l0 and the output from this amplifier I0 is applied to the inputs of a virtual earth feedback amplifier 11 via a resistor 12 and a virtual earth feedback amplifier 13 via a resistor 14. An output terminal 15 connected to the output from the amplifier 11 is provided for the output of the signal from the memory capacitor C which varies in amplitude according to the amplitude of the samples taken, and an output terminal 16 is provided for the output of a vertical shift voltage obtained from the output of the amplifier 10 via a resistor 17 for application to a display device.

An output from the amplifier 13 is fed back to a bias network 20 and one output from this bias network is applied via a lead 21 to an input to the sampling gate 2, a second output is applied via a lead 22 to the output from the sampling gate 2 on the lead 5 which is connected to the input of the amplifier 6, and a third output is applied via a lead 23 to a second input of the differential amplifier 6.

This circuit arrangement provides a waveform sampling device which enables a portion of an input Waveform to be examined for a time which is short compared with the period-of the waveform and a voltage to be stored which is proportional in amplitude to that portion of the input signal, for a time which may be lopg compared with the period of the input waveform. The circuit employs a technique in which each time a sample is taken an output signal is obtained which is dependent upon the difference signal between the previous sample and the sample taken at that time. This avoids the need for generating a stored waveform which originates from zero each time a sample is taken. The system employs a feedback technique to generate an error signal between successive samples.

In operation the gate 2 is opened for a short time at the instant of sampling by the'sampling control pulses which are received over the lead 4 from the generator 3. Unless the voltages applied by the biasing network 20 to the sampling gate 2 via the lead 21 and to the two inputs of the amplifier 6 are such that the sampling gate is balanced an error signal will appear on the lead 5 at the input to the amplifier 6. The output obtained from the amplifier 6 is an inversion of the input. This amplified output from the amplifier 6 is applied to one input of the differential amplifier 8 from the output of which there is obtained an error voltage signal which is related to the difference between the amplitude of the sample being currently taken and the amplitude of the previous sample. The amplifier 8 is a special amplifier which causes a current equal to the voltage at its output divided by the value of the resistor R1 to fiow into the memory capacitor C, whilst the amplifier is gated on so that it conducts, and no current to flow at other impedance noninverting buffer amplifier 10, the resistor 14.

and the virtual earth feedback amplifier 13 to the bias network 20. A signal from the amplifier 10 is also applied via the resistor 12 and the amplifier 11 to the output terminal 15 for use by the monitoring instrument, which is normally an oscilloscope. An output is also obtained on the terminal 16 via the resistors 14 and 17 for controlling the vertical shift of the oscilloscope.

The sensitivity of the system is altered by varying the gains of the amplifiers 6 or 8 and 13 simultaneously while keeping the gain of amplifier ll constant in such a way that the effective loop gain on a sample to sample basis for an error signal is constant and has some value in the range 0.1 to 2.0 dependent upon the noise level transient response required. In normal operation the error signal passing through the sampling gate will charge the input capacitance of the amplifier 6 to a voltage proportional to the error. The capacitor will then start to discharge according to the time constant of the circuit and if this is sufficiently small compared with the gating period, so that increase in this period does not appreciably affect the charge stored in the memory capacitor C,,,, then the effective gain of the system will be independent of the gating period provided that there is no positive feedback around the loop including the amplifier 13. However, since the effective loop gain for an error signal must be of the order of +1 this condition cannot be satisfied unless the loop gain for the feedback signal is much less than this. This is accomplished by feeding the feedback signal to both of the inputs of the differential amplifier 6 through the bias network 20 in such a way that the common mode output signal from the amplifier 6 due to this feedback signal is very low, thus providing a very low loop gain to this signal during the gating period and resulting in only the error signal at the input on the lead 5 being appreciably amplified. Thus if there is no change in amplitude between the sample taken at successive instants the inputs to the differential amplifier 6 will remain constant and there will be no output from the amplifier 6 and no change in level of the output on the terminal 15. It is of course essential that the operation of the scanning voltage in the oscilloscope, the instants of sampling by the gate 2 and the instants of switching of the amplifier 8 are synchronized and the method by which this synchronization is achieved will become clear from the following description of detailed circuit arrangements.

There is thus provided a system which incorporates a differential input amplifier as shown at 6 which ensures that the loop gain for a feedback signal via the amplifier 13 to the gating circuit arranged at the input of the differential amplifier 6 is much less than unity while the gain for an error signalis approximately equal to unity. The provision of a gated amplifier 8 employing feedback to ensure that the charging current supplied to the memory capacitor C,, is strictly related to the error voltage signal, together with the provision of the amplifiersb, l0 and 13 to complete the feedback loop, enables an output signal to be provided which is proportional only to the voltage on the memory capacitor C,,,.

Many samples are required in order to reconstruct one cycle of the waveform if they are to blend together to provide a signal having a smooth line, but it is not necessary to sample each successive cycle of the waveform which may be sampled at successive points in every N" cycle. Furthermore, there is no reason why the sampling should take place successively at points of the waveform which are later in position in the cycle. The sampling may take place with either an increasing or a decreasing time interval and the display arrangements may take account of such sampling in order to display the cycle either in its correct representation or as a reversed display.

Referring to FIG. 2 there is shown within a dotted line 3 a representation of the main features of the time base 3 of FIG. 1. An input applied to the terminal 1 is passed to a trigger circuit 25 which produces a square wave output which is either locked to the input frequency or is triggered by the same point on the input waveform. The output from the trigger circuit 25 is applied to a monostable circuit 26 which is switched on" by the leading edge of the square wave output from the trigger circuit and is switched off" by a reset pulse obtained from a blocking oscillator (not shown). The operation of the blocking oscillator is controlled by a synchronizing pulse dependent upon the frequency of the input waveform. The monostable circuit also includes an arrangement by means of which it is possible to holdoff or interrupt for given periods the trigger pulse output. The output from the monostable circuit 26 is applied to a sawtooth waveform generator 27, which is known as a fast ramp generator. The output from the generator 27 is applied to a comparator 28 and the output from a second sawtooth waveform generator 29 is also applied to the comparator 28. The generator 29 is known as a slow ramp generator. The generator 27 produces a sawtooth waveform which has a leading edge which rises very rapidly compared with the rate of rise' of the waveform from the generator 29. The waveform from the generator 27 is thus said to have a fast ramp whereas the waveform from the generator 29 is said to have a slow ramp. The rate of fall of the trailing edges of the waveforms is, in each case, very fast in the normal manner. The waveforms from the generators 27 and 29 are applied to the comparator 28 at the same level and an output pulse is obtained from the comparator each time that the fast ramp signal intersects the slow ramp signal and it is therefore clear that the repetition frequency of the fast ramp generator must be much greater than the repetition frequency of the slow ramp generator. The start of the fast ramp signal must always occur at the instant that the same reference point on the input waveform being sampled occurs and either the fast ramp generator frequency must be locked to the input signal frequency, which means that sampling will occur at every N samples or the fast ramp signal must be triggered by a particular point on the input pulse waveform which means that locking is not essential but that the triggering point must be very stable. The slow ramp signals are also applied to the X" terminals on the display equipment. An output from the comparator'28 is applied to a fast switch 29a from which a signal is passed to a sampling pulse generator 30 and thence to the sampling gate-2. The slope of the fast ramp may be adjusted in order to vary the readout rate of the pulses applied to the sampling gate. A second output from the comparator may be applied to the blocking oscillator (not shown) referred to above in order to i provide synchronization. An output from the switch 290 may be applied to the distributor 31 from which synchronizing pul-.

ses for use in the system may be obtained. An input on the lead 32 which is related to the repetition frequency of the input waveform is applied to the slow ramp generator 29 in order to synchronize the generator 29.

ln operationan input signal on the terminal 1 is applied to the trigger circuit 25 from which there is obtained a square wave output signal which is either locked to the input frequency of the input signal or is triggered by some point on its waveform. This square wave signal is then applied to a first tunnel diode circuit in the circuit 26, and a square wave output having fast negative going edge is obtained from this circuit with a repetition rate dependent upon the input signal frequency. The output from this first tunnel diode circuit is then applied to a second tunnel diode circuit which is monostable and which has a much larger relaxation time than the first tunnel diode circuit. This second tunnel diode circuit provides a holdoff facility which may be adjusted in order to adjust the rate at which output pulses are obtained and thus the rate at which sampling takes place. As has been explained above this circuit is switched off by a reset pulse obtained from a blocking oscillator (not shown).

The output from the monostable circuit is applied to the fast ramp generator 27 in such a way that a linear high-speed ramp is produced from the outputof the generator 27 during the time that the monostable circuit is in the on" condition.-

A slow ramp voltage from the generator 29, which is synchronized by pulses on the lead 32, is applied to the comparator 28 together with the output from the fast ramp generator 27 so that when the fast ramp voltage reaches the reference voltage provided by the slow ramp waveform a sampling pulse is generated. This sampling pulse is applied to the fast switch 29a and thence to a sampling pulse generator 30 and the gate 2.

The slow ramp generator may in fact produce a waveform of staircase form so. that the ramp is provided by a staircase and a pulse from the blocking oscillator may be used to trigger the slow ramp generator and produce the successive steps in the staircase.

It can thus be seen that there is provided a circuit in which, at a reference time, the leading edge of the high frequency waveform applied at the input terminals 1 triggers the trigger circuit 25 and produces a fast pulse which switches "onthe monostable circuit 26 and causes the fast ramp generator 27, which already has its output near to the level of the slow ramp generator 29, to trigger an output pulse from the comparator 28. The blocking oscillator is also triggered producing the first I the output from the comparator is slightly delayed since it takes slightly longer for the fast ramp to reach the first step level of the slow ramp. This process is repeated until the slow ramp has reached a preset voltage at which point an arrangement in the slow ramp generator resets it to its starting voltage. The complete process now repeats itself and will continue as long as the high frequency waveform is present. There is thus provided a series of samples, the samples being taken at times related to the repetitive frequency of the input waveform but being delayed slightly in a cycle with respect to the position of the sample taken in a preceding cycle. The fast switching stage 29a includes an avalanche transistor which switches very rapidly and the stage produces a number of outputs. One output from this stage can be used to drive the sampling pulse generator stage incorporating a snap-off diode or other fast switching device to provide sampling pulses in the way described above. Alternatively this output can be applied directly to pulse shaping circuits which provide the required sampling pulse or pulses. A second output from this stage 29a drives a pulse generator 31 which may be used to provide pulses to synchronize the slow ramp generator circuit and to reset the fast ramp circuit, to gate the sampling device virtual earth amplifier stage 8 and to blank a cathode-ray tube trace as required. The circuit uses avalanche transistors to switch on the fast ramp generator and in the comparator to provide a rapid output pulse when the fast ramp voltage becomes equal to the slow ramp voltage.

The input trigger stage 25 involves the production of a pulse which switches extremely rapidly. The signal applied to the fast ramp generator has a voltage step with a very short rise time which reverse biases a clamping diode for a capacitor in the generator which capacitor is thereby able to charge and produce the fast ramp output voltage.

Referring to FIG. 3 there is shown the first tunnel diode circuit forming part of the monostable circuit 26 mentioned with reference to FIG. 2. The circuit includes a tunnel diode 35 connected between an input terminal 36 and earth and via an inductance L to the emitter of a transistor 39. The base of the transistor is connected to a voltage V1. The inductor L is connected via an effective constant current or constant voltage generator 37 to an output terminal 38. I

The circuit provides a means for the nonlinear biasing of the tunnel diode under the nonlinear impedance of a transistor. Thus when the tunnel diode 35 is switched by the incoming signal to its low-voltage state the bias supply appears as a constant current generator whilst when the diode is in the high voltage state the bias voltage supply appears as a constant voltage generator. It is required that the value of the effective voltage of the constant voltage generator is such that the diode cannot remain stable in the high voltage state. In the particular circuit arrangement sho n the diode formed by the baseemitter of the transistor 9 provides the nonlinear element and variation of the base potential VI of the transistor 39 enables the effective threshold potential of the source to be varied.

' The impedance of the potential divider at the base of the transistor 39 can be greater than the impedance of a corresponding potential divider network which might be provided in the absence of the transistor by a factor equal approximate,- ly to common emitter current gain of a transistor. Furthermore since the emitter-base capacitance of the transistor is normally considerably less than the capacitance of a high conductance diode which might alternatively be used it is possible for the circuit to sustain oscillations of higher frequency than would otherwise be the case. Synchronization with an input signal may be achieved by modulating the current source via input circuits. The output from the circuit, when signals from the trigger circuit are applied to it, is a square wave signal with a fast negative going edge which has a repetition rate dependent on the input signal frequency.

Referring to FIG. 4 there is shown a circuit which may be used to interrupt, or gate, the incoming train of pulses from the circuit of FIG. 3 for a predetermined interval which may be equal to several cycles of the input waveform. Such an action is also referred to as holding off" the signal. The circuit has an input terminal 40 which is connected via a capacitor C to a tunnel diode 41. A biasing supply is connected at a terminal 42 to the tunnel diode 41 via an inductor Ll. An output may be obtained at a terminal 43 via a capacitor C2.

When the potential at the input terminal 40 rises to a value which is such as to produce a current having-an amplitude which is approximately 20 percent of that of the level of the peak current of the tunnel diode, then the tunnel diode will switch from its low voltage to its high voltage state where it will remain until the current through the inductor L1 has reached such a value that the current through the tunnel diode falls below its valley current. The tunnel diode will then switch back to its low-voltage state and remain there. The bias current via the inductor will increase from the valley current towards its quiescent value with a time constant determined by the value of the inductor L1 and the value of the external bias supply impedance. The potential at the output terminal will exhibit a change from the quiescent value and then return.

In practice, a repetitive waveform will be applied to the terminal 40 and the above cycle of events will occur following the appearance of the signal above the specified amplitude. If however, as is normal, the frequency of the input waveform is such that several pulses appear at the terminal 40 before the time constant of the circuits allow the level specified to be reached, then these successive pulses will not cause any change of potential at the output terminal 43, and these pulses will in fact have been lost. Thus, there is provided a circuit which allows only certain of the pulses in a train to pass at regular intervals, and it is possible to convert a waveform of one repetition rate into an identical waveform of a lower frequency by means of this holdoff circuit.

Referring to FIGS. 5a and 5b there is described an amplifier circuit which may conveniently form a stage in one of the amplif ers for example the amplifier 8 or the amplifier 10 shown in FIG. 1. In FIG. 511 there is shown a known single transistor feedback amplifier including a transistor 45 and resistors R1 and R2, in which the DC output voltage V, is related to the input voltage V,-, approximately by the following equation:

The effective input impedance to a signal applied to the base of the transistor 45 is a function of the feedback ratio and of the common emitter input impedance of the transistor at the collector current used.

It is frequently not convenient to alter V in order to give zero input current for a particular input voltage V,-,,. The use of a common base stage at the input of the amplifier as shown in FIG. 5b enables this to be accomplished by alteration of the base potential of a transistor 46. In FIG. 5b there is shown a transistor 47 having an output terminal V and a transistor 46 the emitter collector circuit of which is included in the feedback path for the transistor 47. The emitter-collector circuit of the transistor 46 is also connected via constant current sources 48 and 49 to an operating supply potential. The input to the circuit is via a terminal V,,,. The input to the base of the transistor 47 is thus provided by a high impedance via the transistor 46 while the input to the circuit at terminal V, appears as a low impedance. The effective input impedance of the amplifier is now a function of the feedback ratio and of the common base input impedance of the transistor 46. Thus it is possible to approach the ideal virtual earth point of the input circuit of the transistor 47 since the input impedance of the transistor 46 is very much less than that of the transistor 47. The arrangement of FIG. 5b makes clear that it is possible to provide an amplifier having a common base input stage 47 and one, or even more than one transistor stage corresponding to "the transistor 46, whichprovides phase inversion between the input current and the output voltage and enables the voltage, corresponding to zero input potential for the amplifier, to be varied by alteration of the base potential of the transistor 46. It

also enables a very low input impedance to be achieved, as explained above, by injecting a current considerably larger than the input signal current into the emitter of the transistor 46 and subtracting an equal or different current from the collector of the transistor 46.

Referring to FIG. 60 there is shown schematically the circuit arrangement of the amplifier 8 in FIG. 1 employing the memory capacitor C,,,. The input to the circuit is between two terminals 51 and 52 and in FIG. 6b there is shown a detailed circuit corresponding to the arrangement of FIG. 6a. In FIG. 6b there are shown two input terminals 51 and 52 by means of which an input signal may be connected to a transistor 53 which, together with a transistor 54, forms a differential amplifier which is gated by means of gating pulses applied to the collector of transistor 53 via a diode 60 from terminals 61 and 62. The output from the base of the transistor 54 is applied to the terminal 55 via the capacitor C,,,. The resistor R1 is connected between the base of the transistor 54 and the negative voltage terminal of the circuit via a transistor 59. The differential amplifier has a very high output impedance which causes a current to flow into the memory capacitor C when the amplifier is gated on. The capacitor current develops a potential across the resistor R, which is applied as a negative feedback signal to a second input of the differential amplifier in such a way that the capacitor current is determined to the first order by the relation in Icm- R1 Furthermore in the arrangement shown in FIG. 6b a pair of transistors 57 and 58 are connected to one terminal of the capacitor C,,, and the current flowing into the memory capacitor when the amplifier is gated off will be the difference between the collector leakage current of the transistor 58, which is gated by pulses applied to the terminals 63 and 64, and the collector leakage current of the transistor 57, andthis current can be less than 0.1 n amperes for a suitable transistor. Thus there is provided an amplifier which allows current to flow into the memory capacitor C,, whilst the amplifier is gated on" and virtually no current to fiow from the output at all other times.

Referring to FIG. 7 there is shown a sawtooth waveform generator circuit which may be synchronized with an incoming signal waveform. The circuit includes a capacitor C, which is charged via a constant current source 74. The capacitor voltage is sensed by a transistor 70 which may in fact consist of one or more transistors connected as a compound emitter-follower presenting a high impedance to the capacitor C, and a low impedance to the output V,,. The base of the transistor 70 is connected via a transistor 71 and a diode D, to the capacitor C,. When the voltage across the capacitor C, exceeds a value, determined by two resistors R, and R together with the forward resistance of the diode D, and the impedance of the base-emitter diode of the transistor 71, the transistor 71 will conduct current into the base of the transistor 70 thereby providing regenerative feedback round the loop including the transistors 70 and 71 and causing the circuit to switch to a state in which it presents a very low impedance to the capacitor C, so discharging it until the voltage at the cathode of D approaches the supply voltage Vs. Two transistors 75 and 76 are connected to provide a feedback circuit so as to ensure that the circuit switches back regeneratively to its high impedance state even when the charging current through the constant current generator source 74 exceeds the sustaining current of the circuit.

As the capacitor C, is discharged the voltages at the base and the emitter of the transistor 76 will rapidly approach the supply voltage Vs, but before this occurs the voltage at the emitter junction of the transistor 75 causes current to flow into the base of the transistor 73 where it is amplified and causes a voltage to be developed across a resistor R in the base circuit of the transistor 71 this will reverse bias the emitter-base junction of the transistor 71 and cause the circuit to switch back to its high impedance state. In addition to allowing a very wide range of charging current to be used this circuit also enables both the maximum and minimum potentials on the capacitor C, to be defined through the potential divider consisting of resistors R R R, and R A terminal 72 is connected to the base of the transistor 71 and, in order to use this circuit as a sawtooth waveform generator, synchronizing pulseswhich consist of short positive pulses at regular intervals are applied to the terminal 72 at times which are coincident with the instant when an additional current pulse is fed into the capacitor C,. This ensures that even when the mean value of the charging current through the constant current generator 74 is fully below the threshold current for the operation of the bistable device formed by the transistors and 71, the circuit will still regeneratively switch when the positive pulse applied to the terminal 72 causes the transistor 71 to become sufficiently forward biased to inject enough current into the transistor for the circuit to switch regeneratively.

The circuit arrangement thus consists of a bistable transistor pair formed by the transistors 70 and 71 arranged in a configuration such that they are able to discharge the capacitor C, when the capacitor potential exceeds the threshold potential of the circuit, an emitter follower output stage 76, and a feedback loop including the transistors 75 and 73 to enable the bistable circuit to reset even when the charging current exceeds the sustaining current of the bistable circuit.

We claim:

1. An apparatus for sampling a continuous repetitive waveform at successive instants of time,.comprising, in combination:

a. an input terminal to which is applied the waveform;

b. a sampling gate, first and second sampling gate inputs and a sampling gate output, said first sampling gate input connected to said input terminal;

c. control means to open said sampling gate at the successive instants;

. a differential amplifier, first and second differential amplifier inputs, a differential amplifier output, said first differential amplifier input connected to said sampling gate output;

. a memory device connected to said differential amplifier output and which is adapted to store a signal which is the difference between successive samples, an output to said memory device from which, in use, an output signal is obtainable corresponding in amplitude to successive points in a cycle of said waveform;

f. a feedback loop including said memory device and said second sampling gate input; and

g. means in said feedback loop to connect to said first and second differential amplifier inputs a feedback signal which is a function of the signal stored in said memory device, whereby the loop gain for the feedback signal is low compared to the loop gain for the signal which is the difference between the successive samples and the signal fed back from the memory device.

2. An apparatus as claimed in claim 1, in which said memory device includes an amplifier, means to gate said amplifier on, a feedback capacitor connected to said amplifier in such a manner that the current fed to said capacitor is directly proportional to the amplitude of the input voltage during the time that said amplifier is gated on and an input circuit which provides a virtual earth point and has a low input impedance.

3. An apparatus as claimed in claim 1, in which said feedback loop further includes a virtual earth amplifier comprising a first transistor connected in common base configuration, a second transistor connected in common emitter configuration, emitter, collector and base electrodes to said first and second transistors, a signal input connected to the emitter electrode of said first transistor, the collector electrode of said first transistor connected to the base electrode of said second transistor, a resistive element connected as a feedback resistance between the collector electrode of said second transistor and the emitter electrode of said first transistor, and a constant current generator connected to each of the collector and emitter electrodes of said first transistor.

4. An apparatus as claimed in claim 1, in which said memory device comprises first, second and third transistors of one conductivity type and fourth and fifth transistors of opposite conductivity type to said one conductivity type, base, emitter and collector electrodes to each of said transistors, and in which said first and second transistors are connected to form a differential amplifier with their emitter electrodes interconnected, a terminal is provided in the collector circuit of the first transistor for connection to a first source of gating pulses, a first signal input terminal is connected to said first transistor base, a capacitor is connected to said second third transistor, the collector electrode of said fifth transistor is connected to said electrical connection, the base electrode of said fifth transistor is connected to thecollector electrode of said fifth transistor and the emitter electrode of said fifth transistor is connected to the base electrode of said fourth transistor.

5. An apparatus as claimed in claim 1, in which the memory device is a capacitor connected to the output circuit of an amplifier.

6. An apparatus as claimed in claim 5, in which the amplifier circlrit including the capacitor is a differential amplifier circuit and in which there is a feedback path for the stored signal to an input to the differential amplifier,means being provided to prevent the discharge of the capacitor during normal operation, whereby the charge on thecapacitor is varied according to the difference between the values of the samples as a function of the change in value of the pulses sampled.

7. An apparatus as claimed in claim 1, in which said control the slow ramp signal.

8. An apparatus as claimed in claim 7, further comprising a sawtooth waveform generator in the time base circuit having a capacitor and a pair of transistors connected to form a bistable circuit and which is arranged to discharge said capacitor and to be triggered in accordance with a synchronizing pulse.

9. An apparatus as claimed in claim 7, further comprising a sawtooth waveform generator in the time base circuit, said sawtooth waveform generator including first and fourth transistors of one conductivity type and second, third and fifth transistors of opposite conductivity type to said one conductivity type, base, collector and emitter electrodes to each of said transistors, a capacitor, a constant current generator connected to charge said capacitor,and in which said first and second transistors are connected to form a bistable pair with the collector electrode of the second transistor connected to base electrode of the first transistor, the collector electrode of the first transistor connected to the base electrode of the second transistor; a terminal for connection to a synchronizing pulse source is connected to the base electrode of the second transistor, a diode is connected between the emitter electrode of said second transistor and one side of said capacitor; said third transistor is connected in emitter follower configuration with its base electrode connected to said one side of the feedback loop with the emitter electrode of said fourth transistor connected to said output terminal, the base electrode of said fourth transistor connected to a tap of a potential divider, the collector electrode of said fourth transistor connected to the base electrode of said fifth transistor and the collector electrode of said fifth transistor connected to the base electrode of said second transistor.

10. An apparatus as claimed in claim 7 having a tunnel diode stage in the time base circuit connected to provide a regular holding off" of the signals applied to it. 

1. An apparatus for sampling a continuous repetitive waveform at successive instants of time, comprising, in combination: a. an input terminal to which is applied the waveform; b. a sampling gate, first and second sampling gate inputs and a sampling gate output, said first sampling gate input connected to said input terminal; c. control means to open said sampling gate at the successive instants; d. a differential amplifier, first and second differential amplifier inputs, a differential amplifier output, said first differential amplifier input connected to said sampling gate output; e. a memory device connected to said differential amplifier output and which is adapted to store a signal which is the difference between successive samples, an output to said memory device from which, in use, an output signal is obtainable corresponding in amplitude to successive points in a cycle of said waveform; f. a feedback loop including said memory device and said second sampling gate input; and g. means in said feedback loop to connect to said first and second differential amplifier inputs a feedback signal which is a function of the signal stored in said memory device, whereby the loop gain for the feedback signal is low compared to the loop gain for the signal which is the difference between the successive samples and the signal fed back from the memory device.
 2. An apparatus as claimed in claim 1, in which said memory device includes an amplifier, means to gate said amplifier on, a feedback capacitor connected to said amplifier in such a manner that the current fed to said capacitor is directly proportional to the amplitude of the input voltage during the time that said amplifier is gated on and an input circuit which provides a virtual earth point and has a low input impedance.
 3. An apparatus as claimed in claim 1, in which said feedback loop further includes a virtual earth amplifier comprising a first transistor connected in common base configuration, a second transistor connected in common emitter configuration, emitter, collector and base electrodes to said first and second transistors, a signal input connected to the emitter electrode of said first transistor, the collector electrode of said first transistor connected to the base electrode of said second transistor, a resistive element connected as a feedback resistance between the collector electrode of said second transistor and the emitter electrode of said first transistor, and a constant current generator connected to each of the collector and emitter electrodes of said first transistor.
 4. An apparatus as claimed in claim 1, in which said memory device comprises first, second and third transistors of one conductivity type and fourth and fifth transistors of opposite conductivity type to said one conductivity type, base, emitter and collector electrodes to each of said transistors, and in which said first and second transistors are connected to form a differential amplifier wIth their emitter electrodes interconnected, a terminal is provided in the collector circuit of the first transistor for connection to a first source of gating pulses, a first signal input terminal is connected to said first transistor base, a capacitor is connected to said second transistor base, a first output terminal is connected to said capacitor, a feedback resistive element is connected between said second transistor base and an electrical connection extending between a second signal input terminal and a second output terminal, a further resistive element is connected between said electrical connection and said first transistor base, the collector electrodes of said third and fourth transistors are connected to said first output terminal, a further terminal is provided for connection to a second source of gating pulses and which is connected to the base of said third transistor, the collector electrode of said fifth transistor is connected to said electrical connection, the base electrode of said fifth transistor is connected to the collector electrode of said fifth transistor and the emitter electrode of said fifth transistor is connected to the base electrode of said fourth transistor.
 5. An apparatus as claimed in claim 1, in which the memory device is a capacitor connected to the output circuit of an amplifier.
 6. An apparatus as claimed in claim 5, in which the amplifier circuit including the capacitor is a differential amplifier circuit and in which there is a feedback path for the stored signal to an input to the differential amplifier, means being provided to prevent the discharge of the capacitor during normal operation, whereby the charge on the capacitor is varied according to the difference between the values of the samples as a function of the change in value of the pulses sampled.
 7. An apparatus as claimed in claim 1, in which said control means to open the sampling gate at successive instants includes a time base having a slow ramp sawtooth waveform generator, a fast ramp sawtooth waveform generator and a comparator, the outputs from the generators being applied to the comparator, whereby output pulses are obtained from the comparator at the instants when the fast ramp signal intersects the slow ramp signal.
 8. An apparatus as claimed in claim 7, further comprising a sawtooth waveform generator in the time base circuit having a capacitor and a pair of transistors connected to form a bistable circuit and which is arranged to discharge said capacitor and to be triggered in accordance with a synchronizing pulse.
 9. An apparatus as claimed in claim 7, further comprising a sawtooth waveform generator in the time base circuit, said sawtooth waveform generator including first and fourth transistors of one conductivity type and second, third and fifth transistors of opposite conductivity type to said one conductivity type, base, collector and emitter electrodes to each of said transistors, a capacitor, a constant current generator connected to charge said capacitor, and in which said first and second transistors are connected to form a bistable pair with the collector electrode of the second transistor connected to base electrode of the first transistor, the collector electrode of the first transistor connected to the base electrode of the second transistor; a terminal for connection to a synchronizing pulse source is connected to the base electrode of the second transistor, a diode is connected between the emitter electrode of said second transistor and one side of said capacitor; said third transistor is connected in emitter follower configuration with its base electrode connected to said one side of the capacitor and an output terminal connected to its emitter electrode; and said fourth and fifth transistors constituting a feedback loop with the emitter electrode of said fourth transistor connected to said output terminal, the base electrode of said fourth transistor connected to a tap of a potential divider, the collector electrode of said fourth tRansistor connected to the base electrode of said fifth transistor and the collector electrode of said fifth transistor connected to the base electrode of said second transistor.
 10. An apparatus as claimed in claim 7 having a tunnel diode stage in the time base circuit connected to provide a regular ''''holding off'''' of the signals applied to it. 